| 摘要 |
PURPOSE:To contrive to improve the integration degree by a method wherein the occupation area of one transistor type memory cell composed of an MIS capacity element as a memory means and an MISFET as a switching means for write and read-out purposes is reduced. CONSTITUTION:An SiO2 film 2 serving as a field insulation film is formed on a semiconductor substrate 1 and selectively removed, and thereafter a thin SiO2 film 2' serving as a gate insulation film is formed. Of this SiO2 film 2', the common region of the switching MISFET, e.g., semiconductor region which is to form a common source is selectively removed. Next, polycrystalline Si layers 3 are formed selectively at the parts serving as the gate electrode and bit line of the MIS capacitor. The polycrystalline Si layers 3 are changed into conductors, the source region 4 of the MISFET is diffusion-formed by heat treatment, and a polycrystalline Si thermal oxide film 3'' having insulation property is formed on the surfaces of the conductive polycrystalline Si layers 3'. Thereafter, the gate electrodes 5 of the MISFET of the conductive polycrystalline Si layers are so formed selectively as to overlap on the gate electrodes 3' and the source region 4 of the MIS capacity element via the thermal oxide film 3''. |
