发明名称 CONTROLLING CIRCUIT FOR USE OF BUS
摘要 PURPOSE:To improve the utilizing efficiency of a communication line, by providing a circuit for setting a bus utilizing right in accordance with a priority order decided in advance. CONSTITUTION:A controlling circuit 9 confirms whether a communication line lis used or not, by detecting circuits 2, 4 and 5. In case when the communication line is not used, the controlling circuit 9 sends out a bus using request signal to the communication line l from a sending-out circuit 1. In this case, a built-in timing circuit is started. The time required for making this timing circuit time-up is set to a different value at each device, and a device whose set time is short is made to have a high priority order. In case when a bus utilizing right obtaining signal is not detected within a set time of this timing circuit, its own bus utilizing obtaining signal is sent out from a sending-out circuit 3. In this way, a device of the highest priority can use the bus in accordance with the priority order, and the bus utilizing efficiency can be raised.
申请公布号 JPS599737(A) 申请公布日期 1984.01.19
申请号 JP19820118120 申请日期 1982.07.07
申请人 YOKOGAWA HOKUSHIN DENKI KK 发明人 AKAI SOU
分类号 G06F13/372 主分类号 G06F13/372
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