| 摘要 |
Asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus (DAC BUS).
<??>Microinstructions can be read out from working memory.
<??>At least one of the processors, in addition to conventional bus interface registers for latching of data, address, commands to be forwarded to the working memory through the bus, is provided with an additional interface register (39), devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. It is further provided with a multiplexer (17) for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus.
<??>A direct path (25) is established between the system common bus and an input set of the multiplexer.
<??>The microinstruction transfer speed from working memory to the processor is enhanced by means of different timing for the data transfer through the bus and the microinstruction transfer through the bus. Whilst in case of data transfer a bus access cycle is started at the end of the processor cycle during which the relevant bus interface register are loaded, in the case of microinstruction read out from working memory, the additional interface register is loaded at the beginning of a processor cycle concurrently with the request of bus access cycle, so that the two may overlap.
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