| 摘要 |
PURPOSE:To perform the high-speed read, by providing a bit line voltage detecting circuit and a precharge time controlling means, which sets a row decoder to the selected state to control the end timing of a precharge pulse, in a CMOS static RAM. CONSTITUTION:A bit line voltage detecting circuit 31 and a precharge time end pulse generating circuit 32 are added to the CMOS static RAM. The detecting circuit detects that a bit line becomes a prescribed potential by precharge; and by this detection output, not only a row decoder 4 is set to the selectable state but also a precharge time end pulse is outputted from the generating circuit 32 to terminate the output of pulses of precharge pulse generating circuit 33. Thus, the precharge time of the bit line is set to a minimum required for date read, and high-speed read is possible. |
