发明名称 TIME DIVISION INTEGRAED S/P CONVERSION CIRCUIT
摘要 PURPOSE:To decrease the mounting space and to reduce the processing time, by producing a serial/parallel converting output corresponding to each channel, storing temporarily the output in an RAM, and obtaining a parallel output of time division at each channel with an output latching the value. CONSTITUTION:An ROM 10 produces a serial/parallel conversion output corresponding to each channel based on a serial data selected at a scanner 16 in response to a channel designation output from a channel generating counter 22, a counter output outputted from a bit counter 18, and a feedback input to the ROM10. Further, this output is written in a prescribed address of an RAM12 designated with a channel designating output from the counter 22 in a prescribed timing and read out in a latch circuit 14. Thus, a parallel data of time devision at each channel is outputted with the latch signal outputted in a prescribed timing from the circuit 14.
申请公布号 JPS598428(A) 申请公布日期 1984.01.17
申请号 JP19820117582 申请日期 1982.07.06
申请人 MEIDENSHA KK 发明人 KURIMOTO TAKATSUGU;MATSUDA TSUTOMU
分类号 H03M9/00;H04J3/00;H04L5/22 主分类号 H03M9/00
代理机构 代理人
主权项
地址