| 摘要 |
In the present invention, image processing is performed at speeds comparable to those achieved in parallel processing without requiring substantially more area on the substrate than that required in serial processing. In this invention, for an NxN processing kernel, N rows of image memory are processed in parallel through a plurality of N floating gate arrays of dimension NxN, N-1 of the data rows from the memory being recirculated through the N floating gate structures before being discarded. Each of the floating gate structures is offset from the adjacent floating gate structure by one row so that the data from memory need be recirculated only once.
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