发明名称 PACKAGE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To realize multi-pin element without increasing the size of package and simultaneously reduce wiring resistance and wiring capacitance by providing the bump for external elecrode to both upper and lower surfaces of package. CONSTITUTION:A bump 2 for external lead is extracted to both upper and lower surfaces of package directly from the region 4 used as the internal lead pattern. The external lead bump can be extracted from desired position, other than the island, cap, and bonding stitch. Thereby, the internal lead 3 can be shortened and wiring resistance and wiring capacitance can also be reduced. Since the external lead bumps 2, 5 are provided in both sides, a number of pins can be increased up to two times under the same area as compared with the conventional plug-in type package or up to several times as compared with DIP and flat package.
申请公布号 JPS598361(A) 申请公布日期 1984.01.17
申请号 JP19820117516 申请日期 1982.07.06
申请人 NIPPON DENKI KK 发明人 HARIGAYA MAKOTO
分类号 H01L23/12;H01L23/498 主分类号 H01L23/12
代理机构 代理人
主权项
地址