| 摘要 |
PURPOSE:To reduce and enlarge a picture at a high speed with a simple circuit constitution, by providing an input buffer, an output buffer, an address counter, a sampling counter, etc. CONSTITUTION:The picture information D1 of a prescribed quantity is fed to an input buffer 10 and transferred for temporary storage to an output buffer 20 in the form of information D2 in response to an input clock signal CK1. These buffers 10 and 20 are addressed by address counters 11 and 21 and driven by clock signals CK1 and CK2, respectively. AND gates 12 and 22 and NAND gates 13 and 23 are connected in series to the counters 11 and 12, respectively, and a sampling counter 30 is connected to the gates 13 and 23. Then a main clock signal MCK is applied to the gates 12 and 22 as well as to the counter 30, and enlarging and reducing commands CC1 and CC2 are supplied to the gates 13 and 23 respectively. At the same time, a preset signal is applied to the counter 30. Thus a picture can be optionally reduced or enlarged. |
