发明名称 PARITY CHECK SYSTEM
摘要 PURPOSE:To make a memory function equivalently with a parity check circuit and to decode and compare the contents of a register effectively, by storing a parity-checked bit in the memory to be accessed by an address data to which a parity bit is added. CONSTITUTION:The lowermost-order output bit of an ROM2 is a parity-checkded bit data are stored in the ROM2 as shown in the figure. When address data ADR-0-ADR-3 are ''0100'', the data to access the ROM2 is ''01000''. The parity- checked bit ''0'' is stored in the lowermost order digit of location ''8'' of the ROM2 using said address data as its addresses to indicate no error. When said data are deformed to ''0110'', the parity-checked bit is turned to ''1'' and the parity error is detected. When the ROM2 is accessed by the prescribed address data, the data are stored in the ROM2 so that the parity-checked bit is ''0'', and if the deformation of one bit is generated in the data, the parity-checked bit is turned to ''1'' and the parity error can be directly detected.
申请公布号 JPS596641(A) 申请公布日期 1984.01.13
申请号 JP19820115681 申请日期 1982.07.03
申请人 FUJITSU KK 发明人 HIROTA YASUO;NODA TAKAHITO;KAMISAKA YUUJI
分类号 G06F11/10;H03M13/00 主分类号 G06F11/10
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