发明名称 LINE MEMORY CIRCUIT FOR TWO-DIMENSIONAL REDUNDANCY SUPPRESSING ENCODER OF FACSIMILE
摘要 PURPOSE:To speed up the operation of the titled circuit by inverting black and white a picture signal indicated by a changing point at the changing point to form a picture signal consisting of two while and black values when the picture signal is outputted from an RAM circuit to an output part such as a recording part. CONSTITUTION:When a picture signal 22 specified by its changing point is stored in an RAM 17 as it is and the picture signal for one scanning is read out from the RAM 17 and outputted to a recording part or the like, a modified read (MR) encoder 19 forms a picture signal consisting of two white and black values at the changing point. The picture signal 22 specified by the changing point is outputted synchronously with a picture signal clock 21. Since an FF 11 in an inversion circuit 10 inverts an output at every leading edge of the picture signal 22 specified by the changing point for example, the output picture signal 23 is indicated by two white and black values. Therefore, the processing is satisfied only by storing the signal 22 specified by the changing point in the RAM 17 and it is unnecessary for the decoder 19 to convert the signal 22 into an output picture signal specified by two white and black values after converting the run length of the changing point address.
申请公布号 JPS596671(A) 申请公布日期 1984.01.13
申请号 JP19820115566 申请日期 1982.07.05
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 KANAYAMA HIDEAKI
分类号 H04N1/21;H04N1/41;H04N1/417 主分类号 H04N1/21
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