| 摘要 |
PURPOSE:To realize a reliable latch circuit, by reading an input signal at the moment of rising of a timing signal, and operating as a Josephson affirmative circuit that holds the read signal and outputs without influenced by subsequent change of input signal. CONSTITUTION:It is supposed that after latching of signal logic 0 at a time t1, signal logic becomes 1 at a time t2. This becomes a sequence that when timing current Ir is applied to the first gate 21, a signal Is is added as gate current Is1, and accordingly, the curve F of threshold value becomes as shown in the figure. That is, it becomes a sequence of change from the state of being biassed at a point B shown by the arrow fc to P' along the arrow fv, and this is no more than change in a blind sector a2. The first gate 21 remains in a state of zero voltage, and a signal current Ig flows out to the ground through right branch 4, and exerts no influence on the second gate 22. By this way, input signal information can be latched affirmatively at the time rising of the timing signal. |
