| 摘要 |
PURPOSE:To attain a high speed processing, by executing addition and subtraction of a floating point without a Recomplement operation. CONSTITUTION:A floating point data is set to input data registers 1-A, 1-B. Zero checking circuits 2-A, 2-B check whether a mantissa is zero or not. Shifting circuits 3-A, 3-B shift the mantissa as necessary. Input selecting parts 4-A, 4-B output an input as it is or inverting it in accordance with a control signal. An exponent comparing part 5, a digit comparing part 6 and an operation decoding part 7 compare an exponent, a digit and a code of an input data, respectively, and those outputs are inputted to an adder input selecting part 8. By an output of this adder input selecting part 8, the input selecting parts 4-A, 4-B and an adder 9 are controlled. |
