| 摘要 |
PURPOSE:To improve the reliability of a line, by catching a transition signal of a transmission signal line by two flip-flops, and separating the signal with logical conditions between the transition signal and a data sampling period signal for decreasing the fluctuation of a time constant. CONSTITUTION:In receiving a data signal TCD, a signal change is caught by flip-flops FFs 4, 5 and a pulse is generated to an EXO being an output of an exclusive OR gate EX. A shift register SR2 is started with this pulse and a data signal RXD is reset at the leading of an output signal QB. When a signal data is ''1'', the data signal RXD is ''1'', and when the signal data is ''0'', the RXD remains ''0''. |
