| 摘要 |
PURPOSE:To reduce a chip size, by connecting two N-MOS transistors (TRs) in series, and applying inversely an input signal inputted to a gate of one TR to the gate of the other TR. CONSTITUTION:The two N-MOS TRs QN1, QN2 are connected in series, the connecting point is used as an output terminal OUT, an input signal Vi is applied to the gate of the TRQN1 and the signal Vi is applied to the gate of the other TRQN2 by inverting the signal at a C-MOS inverter CI. Since the N-MOS TR in which the chip size is decreased in comparison with the P-MOS TR is used, the chip size is decreased without reducing the buffer ability. |
