发明名称 |
OUTPUT LEVEL STABILIZING SYSTEM |
摘要 |
PURPOSE:To prevent the fluctuation in an output level, by utilizing a voltage controlled variable limiter circuit. CONSTITUTION:An output from a digital IC is applied to a variable limiter circuit 1 and its output is applied to a tuning circuit 2 for obtaining a sinusoidal output. The output of the tuning circuit 2 is fed back via a rectifier circuit 3 to control the level of the variable limiter circuit 1. Since the sinusoidal wave output level is stabilized by controlling the level of the variable limiter circuit, the miniaturization is attained. |
申请公布号 |
JPS594307(A) |
申请公布日期 |
1984.01.11 |
申请号 |
JP19820113563 |
申请日期 |
1982.06.30 |
申请人 |
FUJITSU KK |
发明人 |
TANIGUCHI YOSHIHIKO;SUZUKI HAYASHI |
分类号 |
H04B1/76;H02M7/48;H03B11/00;H03G3/20;H03G3/30;H04J1/02 |
主分类号 |
H04B1/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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