| 摘要 |
PURPOSE:To reduce the scale of hardware and to obtain a delay line capable of constituting economically, by constituting the delay line with a read/write memory. CONSTITUTION:The state of switchig of a switching gate 21 is changed depending on a switching signal SW. When the switching signal SW is given with input data (c) inputted, the data (c) is outputted from a buffer register 22 by a clock CLK1. The gate 21 is switched to a feedback bus side at the next period of the clock and data (b) before one block written already in an RAM23 is read and outputted to the input register 22 via an output buffer register 24. Outputs (c), (b), (a) of the register 22 are written in addresses -m, -m+1, -m+2 of the RAM23 and read out at the next clock period. On the other hand, the data before being rewritten in the RAM23 are (b) and (a) at the address -m, -m+1, and an RAM output RAMout based on it is outputted as (b), (a) at an output data OUTBout in response to a clock CLK2. |
