Digital signal processing circuit

摘要

A digital data signal is distorted by means of a low or high pass filter. Quantization of such a signal in accordance with extracted clock pulses will result in a high error rate if a fixed quantization level is utilized due to attenuated voltage swings and a low differential between the signal excursions and the quantization level. The present invention overcomes this problem by means of a shift register connected to an output of a quantization comparator which is clocked by the extracted clock pulses. A weighting circuit is connected between the shift register and one of the inputs of the comparator to suitably adjust the relative quantization level to compensate for the asymmetrical voltage swings caused by the filtering and thereby greatly reduce the data error rate.