| 摘要 |
PURPOSE:To suppress fluctuation of ground level resulting from a momentary heavy current flowing through the power supply lead by providing an auxiliary power supply lead on the layer different from that of the main power supply lead and by short circuiting both power supply leads at least for each output buffer. CONSTITUTION:In the first layer, a logical circuit group 21 is arranged at the inside of semiconductor substrate 11. At the outside thereof, a peripheral circuit group 22 is arranged in such a manner as surrounding the circuit group 21. The Vss power supply lead 13 of ground level is laid in such a way as forming a closed loop along the periphery of the circuit group 22 and substrate 11. In the second layer, the auxiliary Vss power supply lead 16 is laid in addition to the VDD power supply lead 15 of the lower supply level. These power supply leads 15, 16 are laid respectively in such a way as forming the closed loops along the periphery of substrate 11. Moreover, the power supply leads 16 and 13 are short-circuited at the position indicated by circles 33 corresponding to the circuit group 22 comprising at least the output buffer circuit I/O. Thereby, fluctuation of ground level resulting from a momentary heavy current flowing through the power supply leads can be suppressed and mis-operation can be prevented. |
