| 摘要 |
1. Fast, with the aid of insulated-gate field-effect transistors monolithically integrated driver circuit for digital signals, which is connected between a load capacitance (CL) and the output of a stage (S; IM) which is capable of being loaded only with the comparatively small input capacitance (CV; CI) of the driver circuit and, for the purpose of realizing the capacitance ratio of the load capacitance to the input capacitance (C = CL/CV or CL/CI), contains inverters, namely, an output inverter (IA) and a pre-inverter (IV) which, in terms of signal flow, are connected in series, with an enhancement transistor (TA) being provided which, with its source-drain line, is connected in parallel with that of the load transistor (TLA) of the output inverter (IA), with the gate thereof, together with the gates of the load transistors (TLV, TLA) of the inverters (IV, IA), being connected to the output of the pre-inverter (IV), and with the gates of the switching transistors (TSV, TSA) of the inverters (IV, IA) being connected to one another, and with the load transistors (TLA, TLV) of the inverters (IA, IV) being of the depletion type, and the associated switching transistors (TSA, TSV) being of the enhancement type, characterized by the following features relating to capacitance ratios (C) greater than approximately 15 to 30 when realized in accordance with the twophase ratio technique : - for a capacitance ratio part (C1) of about 15 to 30, with C = C1 . C2 being applicable, - the channel widths of the switching transistors (TS...) increase in the direction of the signal flow at least partially from stage to stage in accordance with a geometric progression, - the channel-width to channel-length ratio (W/L ratio) of the enhancement transistor (TA) is almost the same as that of the switching transistor (TSA) of the output inverter (IA), - an intermediate inverter (IZ) is inserted in such a way between the pre-inverter (IV) and the output inverter (IA) that the gate of its enhancement-type switching transistor (TSZ) is connected to the gates of the other switching transistors (TSV, TSA), and that the gate of its depletiontype load transistor (TLZ) is connected to the output of the pre-inverter (IV), while the gates of both the enhancement transistor (TA) and the load transistor (TLA) of the output inverter (IA) are connected to the output of the intermediate inverter (IZ), - the channel width of the switching transistor (TSZ) of the intermediate inverter (IZ) is larger by about the multiplication factor of the geometric progression than that of the switching transistor (TSV) of the pre-inverter (IV), and - for the remaining capacitance ratio part (C2), - there are provided prestage inverters (I1...I4) which, in terms of signal flow, are connected in series, with them being dimensioned to the shortest delay time by keeping constant the quotient of both the input capacitance of the inverter subsequently following within the series and the W/L ratio of the load transistor of the inverter, and with the W/L ratios thereof increasing in the direction of the signal flow from stage to stage in accordance with a geometric progression, - ahead of the input of the driver stage there is disposed a first transfer transistor (TT1) which is controlled by one part (F2) of the two-phase clock signal, and - between the output of the last prestage inverter (I4) and the input of the output stage there is disposed a second transfer transistor (TT2) which is controlled by the respective other part of the two-phase clock signal. |
