| 摘要 |
PURPOSE:To minimize the bus occupation time of DMA by separating actual DMA bus occupation time from the preprocessing or postprocessing of DMA and releasing a bus while one I/O performs the preprocessing or postprocessing of DMA. CONSTITUTION:An MPU board interrupts its operation temporarily and is disconnected froma bus to release the bus when a signal DMAWAT signal goes down to ''L'', and restarts operating when the signal goes up to ''H''; and an MPU bus request part 16 generates a signal for the top priority of bus acquisition. An I/O board causes a conflict between the preprocessing or postprocessing of DMA and I/O access by the sequential circuit of an I/O access and DMA access priority processing part 18. If I/O access to the board itself is caused during the preprocessing or postprocessing of DMA, an I/O access accepting part 19 holds an address temporarily and the DMA is attained after the bus is released to the MPU; and the DMAWAT is held at ''H'' and I/O access to the MPU is carried out. |
