发明名称 Dual-gate deep-depletion technique for carrier-generation-lifetime measurement
摘要 A method for investigating the quality of dielectrically isolated thin film semiconductor layers in inversion-mode MOS devices having dual-gate control capabilities which allow two channels to be created in the semiconductor film. With one channel conducting and a drain voltage providing operation in the saturation region, a step voltage is applied to the gate associated with the second channel which has a transient effect on the current in the first channel. This transient may be analyzed to measure the generation lifetime and other parameters in the body of the device.
申请公布号 US4425544(A) 申请公布日期 1984.01.10
申请号 US19810241307 申请日期 1981.03.06
申请人 THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY 发明人 BARTH, PHILLIP W.
分类号 G01R31/28;(IPC1-7):G01R31/26 主分类号 G01R31/28
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