| 摘要 |
PURPOSE:To obtain a CMOSIC which is useful for an RAM and inverter by providing a P channel enhancement type FET on an N(P) type Si substrate while an N(P) channel enhancement type depletion type FET within a P(N) well. CONSTITUTION:An N<-> type Si substrate 3 is isolated by the channel stoppers PS<+>, NS<+> and an SiO2 thick film 8, a P<-> well 4 is provided, a mask R is provided, the P ion is implanted through a gate oxide film 9 thereby forming the N<-> region, and a depletion current is controlled. The mask R is removed and a poly-Si gate 11 is provided. Moreover the N channel and P channel source, drain 6, 7 and 5 are formed, the suace is covered with SiO2 10 and PSG12 and an electrode 13 is attached. According to this structure, the two P channel elements of RAM using two P channel elements and four N channel elements can be substituted with the N channel depletion type element in the well and thereby an integration density can be improved drastically and a high load resistance depletion type FET having a thin N<-> region can be obtained with good controllability. As a result, an inverter with less power consumption can be structured. |
