| 摘要 |
PURPOSE:To readily control the size of the gates of a memory cell and a peripheral circuit element to optimum values by forming polysilicon layers simultaneously formed with the memory cell and the peripheral circuit element by gate pattern by utilizing respective masks. CONSTITUTION:Only the second polysilicon layer 6 of a patterned peripheral circuit element B side is selectively etched and removed by a plasma etching method of Freon gas, thereby forming a polysilicon layer 9 to become the gate of the element B, and the respective resist pattern 8 is temporarily removed by plasma etching method with oxygen gas. Further, second resist pattern is formed at the peripheral circuit element B side already formed with the polysilicon layer 9 to cover the entirety and at the memory cell A side to cover the prescribed necessary pattern. Then, plasma etching of Freon gas and oxygen gas is repeated, thereby patterning the second polysilicon layer 6, the second gate oxidized film 5, the first polysilicon layer 4 and the first gate oxidized film 3. |
