| 摘要 |
PURPOSE:To support processing in step mode without degrading the performance of an interpreter in normal operation, by providing a means of causing an interruption of a microlevel only in step mode. CONSTITUTION:A step exception (SEXP) bit 13 for some instruction among microinstructions of the interpreter 1 is set on previously during the generation of the interpreter 1. When a step flag 14 is set and the interpreter 1 is activated, the microinstruction whose SEXP bit 13 is set is loaded to a microinstruction register 11 and information on the SEXP bit 13 is inputted to an AND gate to inform a sequence control part 18 of the generation of exception condition. Consequently, microinstructions in an exception analytic routine are read out of an CS21 to a microinstruction register 11 and a step mode processing part 23 starts. |
