发明名称 PRIORITY CONTROL SYSTEM
摘要 PURPOSE:To reflect urgency of time accurately and to decide on the priority of requests for processing from channels connected to an I.O. subsystem by adding processing request order to the channels themselves and providing the function of sending out data. CONSTITUTION:For example, 1-32 in a system model are channels where input/ output devices IO are coupled; and a priority level class is added to the contents of each request for processing and the request for processing is sent to an adapter through the IO. Adapters 101-104 form the lowermost layer of hierarchical structure where eight channels are coupled in parallel, 201-202 form the 2nd layer, and 301 forms the 3rd layer; and requests for processing from the chnnels are passed, one by one, to a memory controller MCU. The MCU402 functions as a processing part for the requests from the channels and connects with a central processing unit CPU and a main storage device MSU to access the MSU401 at requests from the channels 1-32 and CPU403.
申请公布号 JPS593614(A) 申请公布日期 1984.01.10
申请号 JP19820113571 申请日期 1982.06.30
申请人 FUJITSU KK 发明人 OJIRO YOSHIFUMI
分类号 G06F13/362;G06F13/18 主分类号 G06F13/362
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