Integrable semiconductor circuit for a frequency divider

摘要

An integrable semiconductor circuit for a multi-stage frequency divider having a number of master-slave flip-flop cells constructed in current mode logic forming the individual divider stages which are connected in series to a supply voltage and which are accordingly at different levels of the supply voltage has an input stage to which an input signal at an input frequency, and the inverse thereof, are supplied. The input stage is in the form of a differential amplifier having two identical transistors which are connected to a constant current source. The differential amplifier forms the first divider stage, that is, the first master-slave flip-flop, in combination with a first network including a number of transistors and load resistors. The further divided stages do not require an input circuit, therefore each subsequent stage includes only a network corresponding to the network of the first stage. The outputs of the slave portion of the first network respectively control one of the two inputs of the second network (second divider stage) and so on for each subsequent divider stage. The outputs of the master portion are connected through respective load resistors through respective paths leading to the supply voltage external of the networks. The voltage drop of each path is matched to the voltage drop within the chain of networks leading to the supply voltage.