发明名称 TIMER FOR EVALUATION OF COMPUTER SYSTEM
摘要 PURPOSE:To measure the execution time of each part within a CPU with addition of an extremely small quantity of hardware, by providing busy flags and selecting properly one of these flags to start a clock counter. CONSTITUTION:Signals alpha, beta...epsilon showing a working state are supplied to a busy signal register 20 from a function block part which has to measure the execution time within a CPU. The part 20 is connected to an AND gate 60 via AND gates 32-36 and then an AND gate 37. While busy signal selection flags a, b...e are fed to a busy signal selection flag register 31 via a latch 38. These selection flags are connected to the gate 60 via the gates 32-36 and the gate 37. An output of 1 is supplied from the gate 60 when an initialization control bit A in a clock counter 50 is set at 1. Then pulses C are counted until the count value reaches 0. This count value is delivered to buses 11 and 12 via latches 41 and 42, respectively.
申请公布号 JPS593563(A) 申请公布日期 1984.01.10
申请号 JP19820112806 申请日期 1982.06.30
申请人 FUJI DENKI SEIZO KK;FUJI FUAKOMU SEIGIYO KK 发明人 KARATSU YASUSHI
分类号 G06F11/34;(IPC1-7):06F11/34 主分类号 G06F11/34
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