| 摘要 |
PURPOSE:To constitute a titled device so that a control data of a main control storing circuit is stored in a compressed state, and also to simplify a decoding circuit, by forming a control signal by selection and logical processing of plural control data from a sub-control storing circuit. CONSTITUTION:The head address of a main control storing circuit CS by an instruction code OPC is set to an address register CSAR, CS is subjected to access by its address, two control data are read out simultaneously, and the control data selected by gate circuits G1, G2 which are controlled by an output signal of a branch deciding circuit BD is held in a data register CSDR. A sub-control storing circuit CT is subjected to access with contents of an address field (b), as an address signal, and as to this CT, too, two control data are read out simultaneously, and the control data selected by gate circuits G3, G4 which are controlled by an output signal of a selecting circuit SEL is held in a data register CTDR, and becomes a control signal for controlling each part. |
