发明名称 PHASE COMPARISON CIRCUIT
摘要 PURPOSE:To attain the phase comparison even when one of the rise and fall characteristics of a data signal is not steep by applying phase comparison to both the non-inverting and inverting phases of the data signal. CONSTITUTION:A signal (h) is produced at a Q output of a FF 10 at the rise of a data signal (a) and signals (i) and the inverse of (i) are caused in Q and Q outputs of the FF 11 in response to a clock pulse (b). The signals (h) and the inverse of (i) are inputted to an AND circuit 13 and its output signal (k) is a basic pulse in obtaining a phase difference between the signal (a) and the pulse (b). Further, the signal (i) and the signal the inverse of b from the pulse (b) via an inverter 12 enter and AND circuit 14 an its output signal (j) goes to a reference pulse. Then when a signal (l) is caused to the Q output of the FF 16 at the fall (signal the inverse of (a) of the signal (a), signals (m), the inverse of (m) are caused at Q,Q outputs of the FF 17. The signals (n), (o) from AND circuits 18, 19 correspond to signals j, k, the signal (o) is a basic pulse in obtaining the phase and the signal (n) is a reference pulse.
申请公布号 JPS62186611(A) 申请公布日期 1987.08.15
申请号 JP19860028476 申请日期 1986.02.12
申请人 HITACHI CABLE LTD 发明人 IJICHI YOSHIO;NAITO SEIGO
分类号 H03K5/26;H04L7/02;H04L7/033 主分类号 H03K5/26
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