发明名称 CONTROL SYSTEM OF INFORMATION TRANSFER
摘要 PURPOSE:To make data transfer processing efficient, by allowing a bus converter to perform always the transfer on the assumption that fraction data remains in a buffer. CONSTITUTION:First, a transfer controlling circuit 18 supplies the number of an input/output device and the transfer byte position to a buffer 8 in performing data transfer from the 1st to the 2nd bus so as to shift data from a port 9 to the buffer 8. Then, the data in the buffer is transmitted to the 2nd bus. Further, when the data is tansferred from the 2nd to the 1st bus, the started input/output devivce supplies the number of the input/output device and the byte location to be stored at first and transfers the data to the buffer. Then, the data is shifted from the buffer 8 to a port 10.
申请公布号 JPS59721(A) 申请公布日期 1984.01.05
申请号 JP19820110980 申请日期 1982.06.28
申请人 PANA FACOM KK 发明人 HAIDA HIROTOSHI;WADA OSAMU;KATAKURA OSAMU
分类号 G06F13/36;G06F13/40 主分类号 G06F13/36
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