发明名称 GENERATOR OF ACCELERATING AND DECELERATING PULSE
摘要 PURPOSE:To improve the accuracy of motor control and the reliability, by generating an accelerating/decelerating pulse of high speed in response to an optional form of speed curve without requiring complicated adjustments such as zero point and gain adjustments. CONSTITUTION:A processor 12 writes a corresponding bit pattern in a pattern memory 1 through a write circuit 2 according to the speed curve of desired acceleration/deceleration in advance. The processor 12 sets a start address 101 of the pattern memory 1 to an address counter 3 and a stop address 102 to an address coincidence detecting circuit 6. Further, when a flip-flop 4 is set with a start signal 103, an output signal 104 of an oscillating circuit 7 is inputted to a frequency division circuit 9 via an AND gate 8. A frequency dividing signal 105 counts up the address counter 3. When a pattern memory address signal 106 is coincident with the stop address 102, the address coincidence detecting circuit 6 transmits an end signal 111 to the processor 12.
申请公布号 JPS59702(A) 申请公布日期 1984.01.05
申请号 JP19820110037 申请日期 1982.06.28
申请人 HITACHI SEISAKUSHO KK 发明人 ASANO TOSHIROU
分类号 G05B19/02;G05B19/416 主分类号 G05B19/02
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