SHARED MEMORY MULTIPROCESSOR SYSTEM

摘要

SHARED MEMORY MULTIPROCESSOR SYSTEM In a system comprising a plurality of processors interconnected by an inter- processor communication controller (ICC), information is transferred from one processor to another via the ICC. Commands from an originating processor are entered in the ICC and responses from the ICC are returned to either the originating or the terminating processor. The response from the ICC includes the address of the first buffer location and the length of the buffer for holding data to be received from an originating processor or to be transferred to a terminating processor. The data buffers are read by a terminating processor by issuing commands to the ICC.