Method for manufacturing semiconductor devices.

摘要

A method for forming a Bi-CMOS structure, wherein a vertical npn transistor and CMOS transistors are formed on a single semiconductor substrate, is disclosed. After forming a p-type epitaxial silicon layer (33) on a p-type silicon substrate (31) with a plurality of n+-type buried layers (321, 322) therein, n-type wells (351, 352) are formed to extend to the n+-type buried layers (321, 322). Selective oxidation is performed to form field oxide films (41) so as to define an n-type element region for the npn transistor, an n-type element region for the p-channel MOS transistor, and a p-type element region for the n-channel MOS transistor, and a p-type element region for the n-channel MOS transistor. An oxide film (42) as a gate oxide film for the CMOS is formed on the surfaces of all the element regions. After forming a p-type active base region (43) of the npn transistor by ion-implantation of boron, an emitter electrode (46) comprising an arsenic-doped polysilicon layer is formed in contact with the p-type active base region (43). Gate electrodes (471, 472) of the CMOS are formed and have a low resistance due to doping with phosphorus and/or arsenic. Using the emitter electrode (46) as a diffusion source, an n-type emitter region (49) is formed. Boron is then ion-implanted to simultaneously form a p+-type external base region (50) and p+-type source and drain regions (51, 52) of the p-channel MOS transistor. Phosphorus is ion-implanted to form an n+-type collector contact region (53) and n+-type source and drain regions (54, 55) of the n-channel MOS transistor.