| 摘要 |
PURPOSE:To enable decoding for the data independently of sections at the first and latter half bits of the reception series data, by differentially decoding the decoding circuit of FM code. CONSTITUTION:When a timing clock pulse (b) is given to an FF505, the pulse C from the Q output terminal is introduced from an output terminal 504 externally. Further, the Q output signal of the FF505 and the original timing clock pulse (b) are given to an AND gate 509 to output the clock pulse (d) for the selection of the latter half bit. Further, this pulse (d) is given to an FF506 to select the latter half bit of the reception series data. The signal selected at the FF506 is given to an FF507 and a signal delayed by a period T is outputted Q. Further, the Q output of the FFs 506 and 507 is in EXOR at a gate 508 and inverted at an inverter 511 for decoding. |
