发明名称 CONTROL SYSTEM FOR PARALLEL COMPUTER COMMUNICATION
摘要 PURPOSE:To prevent the easy occurrence of a congestion state of communication by performing the control so that a message transmitting direction is decided based on the value of a residual capacity table of an adjacent processor reception buffer when a transmission request is produced. CONSTITUTION:Each processor 10 contains a residual capacity table 14 of an adjacent processor communication buffer and has a size Ri (i=1-4) of an idle area of a reception message buffer 17 of the adjacent processor 10 in accordance with the communicating direction of the processor 10. The table value Ri is initialized in the maximum size of the buffer 17 in an initialization state where a power supply is applied. If a message transmitting request is received from a transmission request part 15, a message transmitting direction deciding part 13 is started. The part 13 reads the message address and decides plural transmitting directions. Then the values of the corresponding capacities R3 and R4 are read out of the table 14 and the message is transmitted in the SOUTH with R3<R4 and in the EAST with R3>R4 respectively. While either direction is selected according to the priority when R3=R4 is satisfied.
申请公布号 JPS63301351(A) 申请公布日期 1988.12.08
申请号 JP19870138422 申请日期 1987.06.02
申请人 FUJITSU LTD 发明人 HORIE KENJI;IKESAKA MORIO
分类号 G06F15/16;G06F15/177;G06F15/80 主分类号 G06F15/16
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