发明名称 DELAY CIRCUIT WITH INTRINSIC SAFETY
摘要 A total security time-delay circuit useful in railway communications, for example, provides a series of output pulses after a specific minimum interval in response to a direct voltage applied to an input of the circuit, the minimum interval being maintained even in the event of circuit component malfunctions. A pulse generator connected to the circuit input provides a series of pulses to control a first contact breaker which switches the primary winding of a transformer to partially discharge a capacitor which is series-connected to the primary winding. The capacitor charges through a resistive network of a transformer secondary winding circuit which includes a second contact breaker having a control terminal connected to the transformer secondary winding and operable to provide output pulses when the capacitor discharge reaches a sufficient intensity. A grounded Zener diode connected to a junction of the resistive network and a switch terminal of the second contact breaker ensures that the time delay of the output pulses is not reduced below the minimum interval, even in the event of malfunctions in other circuit components.
申请公布号 ZA8302364(B) 申请公布日期 1983.12.28
申请号 ZA19830002364 申请日期 1983.03.31
申请人 JEUMONT-SCHNEIDER 发明人 CAMUS ETIENNE
分类号 H03K17/28;H03K17/60 主分类号 H03K17/28
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