| 摘要 |
PURPOSE:To decrease the data transmitting time, by using at least two memories to store the unit data related to these memories and reading the related stored unit data in parallel out of those memories. CONSTITUTION:A CPU 1 is connected to RAM 4 and 5 via an address changeover switch 2 and an alternate switching circuit 3. A reading control circuit 6 is connected to the memories 4 and 5 via address changeover switches 7 and 8. The switch 2 and switches 7 and 8 are controlled alternately. The memories 4 and 5 are connected to a display via a data bus 9. The unit data related to RAM 4 and 5 are stored, and then these unit data are read out of the RAM 4 and 5 in parallel to each other. |
