| 摘要 |
PURPOSE:To reduce the frame period and to improve the transmission speed by providing a bit addition means adding a start bit changing from the 1st level to the 2nd level at a 1/2 period of 1-bit to the head of a bit serial data outputted from a shift register. CONSTITUTION:The Q output of a D flip-flop 43 included in a start bit generating circuit 4 goes to an H level and the inverse of Q output goes to an L level in the timing when the output of an AND gate 3 goes to an H level. The inverse of Q output is given to one input of an AND gate 5 and a signal of L level is outputted for 1/2 period of 1 bit from the output of the AND gate 5. On the other hand, the 1st bit data D1 is outputted via the AND gate 5 from an output terminal QC of a shift register 2 when next clock pulse is given to shift registers 1, 2 after a start bit being at an L level for the 1st 1/2 period of 1 bit and at an H level for the next 1/2 period is outputted from the shift register 2. Thus, a data is sent continuously in the unit of frames at the 1/2 period of 1 bit. |
