发明名称 PULSE DEFECT PHASE DETECTION CIRCUIT
摘要 PURPOSE:To eliminate erroneous operation and erroneous inoperation even if the frequency of a used power source is largely varied by adding a simple logic circuit to the defect detector of an APPS of a narrow band double pulse output. CONSTITUTION:Only a main pulse is produced by an AND circuit 32-a from double pulses, and is set to the set signal of a flip-flop 31, and the main pulse of the phased delayed by 120 or 180 deg. from the previous signal is set to the reset signal of the flip-flop 31. The AND of the set signal of the flip-flop 31 and the output of an oscillator 33 is taken by the AND circuit 32-a, and the output is counted by a counter 34. A comparator 35 outputs a signal when the counted value of the counter 34 exceeds the prescribed value, and the signal is externally outputted through an output circuit 36.
申请公布号 JPS58224557(A) 申请公布日期 1983.12.26
申请号 JP19820106867 申请日期 1982.06.23
申请人 HITACHI SEISAKUSHO KK 发明人 OOSONE TADASHI
分类号 G01R29/02;H02M1/00;H02M1/084 主分类号 G01R29/02
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