| 摘要 |
PURPOSE:To discriminate accurately logic of signal by eliminating an input signal not continuous for a prescribed time as noise for eliminating the effect of noise and external disturbance. CONSTITUTION:Inverter circuits L1-L6 have a hysteresis characteristic and constitute a sample holding circuit with gates G. For example, a reset signal is inputted to the inverter L1 from an input signal terminal T1. The inverter circuit output is sample held with the 1st pulse train alpha having a prescribed pulse repetitive period and this output is inputted to the 1st delay circuit D1. The 2nd pulse train beta has the same period as that of the pulse train and is delayed for a prescribed phase than the pulse train alpha and the delay circuit outputs the input signal with a delay for a pulse period's share by the sample holding with the pulse trains beta and alpha. The same delay circuits D1-D2n are connected in cascade to discriminate the logic of the input signal with the logical product of the outputs of the delay circuits. |
