| 摘要 |
A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level.
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