发明名称 MEMORY CIRCUIT
摘要 PURPOSE:To attain high speed, by controlling an output voltage of a delay circuit detecting a potential of an upper word line and the amount of current supplying to a lower word line by means of the 1st clamping means at the selection of the upper word line and the 2nd clamping means at non-selection. CONSTITUTION:The potential variance of the upper word line Lxo', a resistance ratio variance of resistors R201, R202 and further a base potential variance of a transistor(TR)Q204 due to the collector current variance of the TRQ202 are eliminated by providing a TRQ300 in a bipolar, and the current variance between delay circuits 30a and 30b is reduced. When the upper word line Lxo' is in a non-selection potential, the current of the lower word line depends on the clamping voltage VLCL. The control is done with the 1st clamping voltage when the base potential of the TRQ204 is selected and with the 2nd clamping voltage at non-selection, thereby attaining high speed.
申请公布号 JPS58222487(A) 申请公布日期 1983.12.24
申请号 JP19820103824 申请日期 1982.06.18
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAGUCHI KUNIHIKO;HONMA NORIYUKI
分类号 G11C11/414;G11C11/415 主分类号 G11C11/414
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