发明名称 MULTIPLEX PROGRAMMING PROCESSING SYSTEM
摘要 PURPOSE:To process plural programs in parallel without using a monitor program, by forming plural interrupting levels a line clock signal from a commercial power supply. CONSTITUTION:An interruption controller 3 switches to a 1/5 or a 1/6 frequency division circuit via a switch 4 depending on the power supply frequency of 50Hz or 60Hz. Further, two interruption signals having a different level are inputted to a microcomputer 7 in response to each clock. The computer 7 is incorporated with the 1st interruption program, the 2nd interruption program and a background program. Further, the programming is done from the 1st interruption program having a high interruption level and then the 2nd interruption program is executed. The repetition of the program depends on the number of set channels and the clock frequency.
申请公布号 JPS58222351(A) 申请公布日期 1983.12.24
申请号 JP19820106352 申请日期 1982.06.21
申请人 SHIMAZU SEISAKUSHO KK 发明人 ISHIDA MASARU;SHIMIZU KIYOSHI
分类号 G06F9/46;G06F9/48 主分类号 G06F9/46
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