| 摘要 |
PURPOSE:To improve the reliability of one transistor(TR) drive RAM, by providing an active pullup circuit connected to bit lines and keeping the potential of high potential bit lines to a prescribed potential and generating clocks with the drive clock generating means after write mode. CONSTITUTION:Titled device provids word lines WLi, WLj, bit lines BL0, BL0', BL1, BL1' memory cells cell00..., sense amplifiers SA0, SA1, active pullup circuits AP, APII, and the drive clock generating meas 100. The circuit AP is activated with a drive clock phiA at the readout mode and the circuit APII is activated with a clock phiB at the write mode. Thus, the high level of the bit line BL0' is guaranteed with the page mode in succession with the write mode, and even if the period of the page mode is longer, the active pullup circuit APII is activated repetitively, and the bit lines are brought to a high level even if inverse information written in, allowing to improve the reliability. |
