| 摘要 |
PURPOSE:To shorten an access time and reduce power consumption by introducing a hierarchical structure to the address system and stored data detecting system. CONSTITUTION:The adjacent two block pairs are selected by a higher-ranked row decoder 14, only a lower-ranked docoder 15 between such block pairs is activated, other lower-ranked decoder are power-cut, and an output is fixed to non- active level. The activated lower-ranked row decoder selects one of large blocks 12, namely, a row of small block and charges a row drive line 4 corresponding to the row up to the active level. Therefore, memory cell accumulation data of the selected row is transmitted to the lower data line 5a which is a bit line and only the lower data line 5a which is one bit line is connected to a sense amplifier 9a within a small block 13 owing to a multiplexer 7a which has received an output of lower-ranked column decoder. |
