| 摘要 |
PURPOSE:To attain multiaccess, by a single interface by using a buffer to fetch parameters into the interface as an FIFO buffer memory so as to be enabled to cope with asynchronous access to plural IOs. CONSTITUTION:Before a command and data are written in a packet buffer 202, a CPU writes a packet buffer writing request command IC to an interface in a packet buffer 201. Since the buffer 201 is an FIFO buffer, the CPU can write another request asynchronously if the access is requested to a different IO. The interface takes out the ICs from the FIFO buffer and processes them successively. If an IC is a buffer writing request, the interface selects a corresponding vector from a vector table 206 by a vector selecting logic 207 and sets up the selected vector in a vector register 203 to interrupt the CPU. |
