| 摘要 |
PURPOSE:To obtain failure safeness economically with a small number of parts by using parts for a general comparator and adopting total monitoring system using two pairs of CPUs. CONSTITUTION:An output from a period signal generating circuit 4 having a period T is inputted to interruption input circuits or data input circuits in respective CPUs 1, 2. Data outputted from these CPUs 1, 2 are inputted to a comparator 3 to detect the coincidence or inconsistency of both data and the coincident or inconsistent output is inputted to the data input circuits of respective CPUs 1, 2 and also inputted to a failure output circuit 5 to detect no change of an output from the comparator 3. If only the CPU 2 is delayed for a fixed period at its starting of processing after starting both CPUs 1, 2 by a period signal, both CPUs 1, 2 are prevented from similar malfunction even if an error due to a common mode noise is generated and the failure can be detected by the comparator 3. |
