发明名称 COMMUNICATION CONTROLLING SYSTEM BETWEEN PROCESSORS
摘要 PURPOSE:To execute efficiently communication between processors so that a communication bus is not locked uselessly, by providing a communication buffer on the processor, and also providing a communication controlling circuit for operating and comparing the maximum word number, the present word value and the requested word number of the communication buffer of every processor and informing a state of the communication buffer to the communication origin processor, on a centralized control device for controlling the communication. CONSTITUTION:When a processor 1 generates a condition for communicating the information of an R word to a processor 2, the processor 1 checks a state of a communication bus 5 through a control line 26, to a bus controlling circuit 7 for controlling a state of busy or idle of the communication bus 5, sets it to a busy state by locking it when it is opened, and thereafter, checks an idle degree of a communication buffer 11 by the control line 26, to a communication controlling circuit 16 for controlling a state of the communication buffer 11 of the communication destination processor 2. If the idle degree exceeds an R word, the communication controlling circuit 16 informs the idle state to the processor 1 through the control line 26. When the idle state is informed, the processor 1 sends communicating information to the communication buffer 11 through the communication bus 5.
申请公布号 JPS58220536(A) 申请公布日期 1983.12.22
申请号 JP19820102309 申请日期 1982.06.16
申请人 NIPPON DENKI KK 发明人 TORII YOSHIHARU
分类号 H04L12/407 主分类号 H04L12/407
代理机构 代理人
主权项
地址