发明名称 TESTER FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To enable testing of an optional circuit in an optional testing period, by detecting the dissidence of an expected value signal and the output of an integrated circuit, etc., and blocking the output of a dissidence circuit during said period. CONSTITUTION:The dissidence between the output of an expected value signal and the output of an integrated circuit is detected with a dissidence circuit 10, and the period since the rise of the expected value signal until the rise of the output of the integrated circuit as well as since the fall of the expected value signal until the fall of the output of the integrated circuit are detected with an edge extraction circuit 14, and the output of the circuit 10 is blocked with an edge removing circuit 13 during said detection periods. Then, the integrated circuit of optional constitution is tested without receiving the limit in the test period by a strobe signal.
申请公布号 JPS58221177(A) 申请公布日期 1983.12.22
申请号 JP19820104574 申请日期 1982.06.17
申请人 TOKYO SHIBAURA DENKI KK 发明人 AOKI KAZUHIDE
分类号 G01R31/28;G01R31/317;H01L21/66 主分类号 G01R31/28
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