Method and arrangement for demodulation of a binary frequency-modulated signal

摘要

A high-stability demodulator is to be produced at particularly low component cost. The clock frequency of a clock generator, amounting to a high integral multiple of the bit frequency, is counted with a second divider and evaluated once a specified counter reading has been attained; this counter reading corresponds to a frequency which lies between the two signal frequencies. The second divider is reset with each edge of the binary frequency-modulated signal and is stopped once the specified counter reading has been attained. The attainment or non-attainment of the specified counter reading is fed as a logical "high" or "low" to the data input of a data flip-flop and is transferred with each edge of the binary frequency-modulated signal to the output of the data flip-flop. A first divider divides the clock frequency of the clock generator down to the bit frequency and is reset with each edge of the output signal of the data flip-flop.